General Summary :
Qualcomm is a world leader in wireless technologies and a driving force behind the connected world of the future. As a Senior RTL Design Engineer , you will be at the core of Qualcomm's SoC development efforts, working on high-performance, power-efficient, and scalable logic designs for next-generation wireless and computing solutions.
You will contribute to defining and implementing complex digital designs that are integral to Qualcomm's industry-leading SoCs. This role offers the opportunity to work with some of the brightest minds in the industry, pushing the envelope on performance, power, and silicon complexity.
Minimum Qualifications :
- Bachelor's degree in Computer Science, Electrical / Electronics Engineering, or a related field and 6+ years of hardware engineering experience
- OR
- Master's degree and 5+ years of experience
- OR
- PhD and 4+ years of experience
Required Skills & Experience :
12+ years of experience in RTL design , micro-architecture , and logic design for large-scale SoCsHands-on expertise in Verilog / SystemVerilog for design and simulationProven track record in SoC architecture , integration , and synthesisStrong working knowledge of :AMBA protocols (AXI, AHB, APB)Clocking / reset / debug architecturesCommon SoC peripherals (USB, PCIe, SDCC)Experience in low-power SoC design , including multi-voltage and power domain handlingHands-on with multi-clock domain design , asynchronous interfaces , and related challengesExperience with synthesis tools such as :Synopsys Design CompilerCadence GenusSynopsys Fusion CompilerDeep understanding of timing analysis and STA conceptsFamiliar with PrimeTime or equivalent toolsExposure to constraint development , timing closure , and design convergenceStrong collaboration skills to work with DFT, PD, and STA teams during integration and signoffPreferred Qualifications :
Experience in low-power techniques like power gating, clock gating, and multi-mode / multi-corner (MMMC) analysisUnderstanding of DFT concepts and how RTL decisions impact testabilityPrior experience in developing reusable design components or IPsFamiliarity with version control and design flow automation using scripting (TCL, Python, Perl)Principal Duties and Responsibilities :
Define, implement, and verify micro-architecture for new features within Qualcomm SoCsDevelop high-quality, reusable, synthesizable RTL code using Verilog / SystemVerilogCollaborate with cross-functional teams (DFT, PD, STA, Architecture) to ensure timing, functionality, and power goalsDrive synthesis and timing convergence activities through the full lifecycle of SoC developmentPerform debug and root cause analysis for functional and timing issuesContribute to the improvement of design flows, methodologies, and best practicesReview and maintain technical documentation , design specifications, and timing constraintsSkills Required
Synthesis, Usb, SOC design, Timing Analysis, Physical Design, Verilog