RTL Design Engineer

Work closely with the verification team and review verification plan mapping with the specification, Work with product teams to evaluate customer requirements related to quality, functional safety, and automotive reliability, Work closely with the Functional Safety and internal development teams on projects and task planning, progress tracking and reporting, Key Qualifications

Must have BSEE in EE with 5+ years of relevant experience or MSEE with 4+ years of relevant experience, Must have proven experience working on Automotive SoCs / Digital IPs, Must have proven experience working of one or more of protocols at the IP level : DDR / PCIe / UCIe, Hands on experience with architecting / micro-architecture / detailed design from functional specifications, Hands on experience with Synthesizable Verilog / System Verilog RTL coding for ASIC designs and Simulation tools, Lint, CDC, synthesis flow and static timing flows, formal checking, etc experience, Working knowledge / experience TCL, Perl, Python is added advantage, Has a solid desire to learn and explore new technologies, Performs in project leadership role & guides more junior peers with aspects of their job, Frequently networks with senior internal and external personnel in own area of expertise, Proficient in English, Formal training in ISO 26262 is preferred, Experience in qualifying systems with embedded hardware to various ISO 26262 ASIL levels up to ASIL D

Experience with various ISO 26262 work products such as DFMEA; FMEDA; DFA

Inclusion and Diversity are important to us

Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, gender identity, age, military veteran status, or disability,

Skills Required

Pcie, Sta, LINT, cdc, Python