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Cadence System Design and AnalysisBengaluru, Karnataka, India21 days ago
Job description
12-14 yrs of work experiences in VLSI domain with Master’s / bachelor’s degree in engineering Strong expertise in Verilog, HVL(SV, Specman e) with UVM / OVM / eRM methodology Expertise in assertions development / closure, constraint randomization, functional and code coverages, formal verification Expertise in test-bench development Strong RTL and GLS (w / or w / o SDF) sim debug skills Should be able to manage project schedule and delivery independently
Should be good in Perl / Tcl scripting and automation
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Design Verification • Bengaluru, Karnataka, India
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