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Sr Principal RTL Design Engineer
ConfidentialBengaluru / Bangalore10 days ago
Job description12+ years of experience in ASIC design Proficient in Verilog coding, RTL design and complex control path and data path designs Knowledge of any of the interface Protocols like UCIe, PCIe, USB, MIPI(DPHY), HDMI / Display, Ethernet, SATA Knowledge of RTL checks ex- LINT, SDC, CDC Familiar with synthesis flow, LEC and timing constraints Experience in writing Verilog testbench and running simulations.
Skills Required
Rtl Design, Coding, Usb, Verilog, Ethernet, Pcie, RTL, ASIC Design, Sata, Principal
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Rtl Design Engineer • Bengaluru / Bangalore
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