Principal Engineer - Design Enablement, Compact modeling.

Your Job :

• The role requires a strong background in semiconductor device physics. The candidate should be familiar with the electrical behaviors of semiconductor devices (DC / low frequency, RF / high frequency, noise, mismatch, etc.), and the types of test structures that are needed to characterize them.
• The candidate should be able to apply his / her knowledge of semiconductor device physics in a practical compact model extraction scenario, such as being able to analyze and explain the trends in the data, being able to distinguish real trends from noise , associate various physical phenomena with the observed trends, submit electrical characterization requests, extract various compact modeling parameters, do various QA checks and submit the model for release.
• The candidate should also be able to do design and layout of test structures; be able to correlate device cross section with layout; do various kinds of simulations in Cadence ADE; be proficient in writing python scripts for doing model parameter extraction, data analysis and QA; have knowledge of industry standard compact model families and parameter extraction tools / methodologies; have knowledge of Verilog-A and be able to write Verilog-A models; and be able to field customer queries pertaining the model.

Other Responsibilities :

Required Qualifications :

Skills Required

Python Scripting