Sr. Design Engineer

Development and support of ASIC tech files and development of ASIC flows / methodologies. Enabling RTL2GDSII tools for placement / routing and Timing to support new foundry nodes. Physical designs (RTL to GDSII) of test vehicles to evaluate developed tech file and RTL2GDSII flow / methodology. Regular Interaction with customer during techfile and flow development. Timely tracking of issues and resolving customer support issues. Debug the complex design issues and help the design and CAD teams in PDK and flow deployments.

BTech / BE / MTech / ME / MSc in Electronics / Computer science with Industry experience in ASIC PDK kit / Physical design / ASIC Design automation role.

Hands-on experience with Synopsys and Cadence Place and Route tools, Timing tools, Floor planning, IR Drop and Physical verification.

Should have good understanding of Verilog / VHDL.

Exposure to low power techniques and PPA analysis is desired.

Knowledge of tcl and perl scripting is a must. Strong presentation and communication skills within an international environment.

Skills Required

Floor Planning, Cadence, Synopsys