DFT Static Timing Lead

Will have a passion for modern, complex processor architecture, digital design, and verification in general. You are a team player who has excellent communication skills and experience collaborating with other engineers located in different sites / time zones. You have strong analytical and problem-solving skills and are willing to learn and ready to take on problems.

KEY RESPONSIBILITIES :

• Implementation and verification of DFT architecture and features in NBIO IP and Subsystems
• Scan Network, Memory BIST logic generation and implementation
• Create and maintain DFT timing constraints
• Collaborate with Design, Physical Design (PD) and Static Timing Analysis (STA) teams
• Provide technical support to SoC and Post-Si teams to ensure successful bring up and enhance yield learning
• Mentor and coach junior engineers

PREFERRED EXPERIENCE :

Skills Required

Physical Design, Dft, Jtag, Perl, Verilog, Soc, Python, Technical Support