Leadsoc Technologies - DFT Lead

Job Title : DFT Lead

Location : Bangalore Urban, Karnataka, India

Job Description :

Leadsoc Technologies is seeking a highly motivated and experienced DFT (Design for Test) Lead to join our growing engineering team. As a DFT Lead, you will be responsible for leading and executing DFT activities for complex SoCs, ensuring high test coverage and manufacturability. You will work closely with design, verification, and physical design teams to implement DFT strategies and :

• DFT Strategy and Planning : Develop and implement comprehensive DFT strategies for complex SoCs, considering test coverage, area overhead, and power consumption.
• DFT Architecture : Define and implement DFT architectures, including scan insertion, ATPG, memory BIST, logic BIST, and boundary scan.
• Scan Insertion and ATPG : Perform scan insertion, generate ATPG patterns, and analyze fault coverage.
• Memory BIST and Logic BIST : Implement and verify memory BIST and logic BIST solutions.
• Boundary Scan : Implement and verify boundary scan (JTAG) functionality.
• DFT Verification : Develop and execute DFT verification plans to ensure the correctness and effectiveness of DFT implementations.
• Collaboration : Work closely with design, verification, and physical design teams to integrate DFT into the design flow.
• Tool Expertise : Proficiently use industry-standard DFT tools from vendors like Synopsys, Cadence, and Mentor Graphics.
• Documentation : Create and maintain detailed DFT documentation, including specifications, test plans, and reports.
• Mentoring : Mentor and guide junior DFT engineers.
• Test Pattern Validation : Work with ATE engineers to validate test patterns on silicon.
• Failure Analysis : Assist in failure analysis and debug of silicon failures.

Qualifications :

Technical Skills :

(ref : hirist.tech)