Job Title : DFT Engineer
Job Description : Responsibilities :
- Develop and implement DFT architectures including scan insertion, ATPG, memory BIST, and boundary scan.
- Generate and validate ATPG patterns for stuck-at, transition delay, and other fault models.
- Perform memory BIST insertion, simulation, and verification.
- Work with physical design team to resolve DFT-related issues such as routing congestion and timing violations.
- Develop and maintain DFT scripts and flows.
- Participate in silicon bring-up and debug.
- Collaborate with design and verification teams to ensure DFT requirements are met.
- Document DFT specifications and implementation details.
- Evaluate and improve DFT methodologies.
- Mentor junior engineers.
Required Skills and Experience :
Bachelor's or Master's degree in Electrical Engineering or Computer Engineering.Strong understanding of DFT concepts and methodologies including scan insertion, ATPG, memory BIST, and boundary scan.Experience with industry-standard DFT tools such as Synopsys TestMAX, Mentor Tessent, or Cadence Encounter Test.Proficiency in scripting languages such as Perl, Python, or TCL.Experience with Verilog or VHDL.Strong problem-solving and analytical skills.Excellent communication and teamwork skills.Experience with low power DFT techniques is a plus.Experience with fault simulation and diagnosis is a plus.(ref : hirist.tech)