Softpath Technologies - Static Timing Analysis Lead

Job Title : STA Lead Full-Chip Static Timing Analysis

Experience Required : 8+ Years

Location : Bangalore, India

Job Mode : Work From Office (WFO)

Industry : Semiconductors / VLSI / ASIC the Role :

We are looking for a highly skilled and experienced STA Lead Engineer to join our SoC / ASIC design team in Bangalore. As an STA Lead, you will be responsible for driving timing closure and sign-off at the full-chip level, working with cross-functional teams to ensure first-time-right silicon.

This role demands expertise in Static Timing Analysis (STA) at both block and top levels, deep knowledge of multi-mode / multi-corner (MMMC) analysis, and experience working with advanced technology nodes (7nm, 5nm, and below). You will take complete ownership of full-chip timing constraints, analysis, ECO closure, and sign-off processes.

This is a key leadership position, suitable for someone who thrives in a fast-paced, high-complexity semiconductor environment and enjoys solving deep technical challenges while collaborating with a world-class engineering team.

Key Responsibilities :

• Lead full-chip static timing analysis across multiple modes and PVT (Process-Voltage-Temperature) corners.
• Take full ownership of top-level SDC (Synopsys Design Constraints) generation, validation, and continuous refinement.
• Collaborate closely with block-level STA, synthesis, physical design, DFT, and clock architecture teams to drive convergence and timing closure.
• Identify and resolve timing violations (setup / hold) using engineering change orders (ECOs), floorplan improvements, and clock optimization strategies.
• Perform MMMC timing analysis covering OCV, AOCV, and POCV variations to ensure robust and accurate results.
• Integrate STA reports from various blocks and carry out hierarchical full-chip STA and timing sign-off.
• Partner with DFT engineers to analyze and fix scan shift timing, capture timing, and at-speed test paths.
• Develop and maintain automation scripts in Tcl, Perl, or Python for report generation, violation tracking, and metrics dashboards.
• Define and communicate timing budgets and constraints to IP / block owners and ensure adherence throughout the design cycle.
• Work with EDA vendors and foundries to address tool issues, model inaccuracies, and sign-off guideline updates.
• Maintain documentation, best practices, and templates for STA methodology across Skills and Qualifications :
• Bachelors or Masters degree in Electronics, Electrical, or Computer Engineering.
• 8+ years of hands-on experience in Static Timing Analysis with a focus on full-chip timing convergence.
• Strong working knowledge of Synopsys PrimeTime, SDC, and timing ECO flows.
• Proven expertise in hierarchical STA, MMMC analysis, and variation-aware timing closure (OCV / AOCV / POCV).
• Solid understanding of digital design principles, clock tree architecture, floorplanning, and DFT timing.
• Proficiency in scripting languages like Tcl, Perl, and Python.
• Experience with advanced technology nodes (7nm, 5nm or lower) and familiarity with foundry constraints and sign-off requirements.
• Strong analytical and problem-solving skills with a detail-oriented approach to debugging complex issues.
• Excellent communication skills and the ability to coordinate across cross-functional global Qualifications :
• Exposure to multi-die or chiplet-based SoC integration is a strong plus.
• Prior experience in leading a team of STA engineers or mentoring junior members.
• Familiarity with static IR drop, crosstalk, and noise-aware STA.
• Understanding of low-power techniques (UPF / CPF-based flows).

Why Join Us ?

(ref : hirist.tech)