Fiori Technology Solutions - Lead DFT Engineer

Job Description :

We are looking for a highly experienced DFT Lead Engineer to take ownership of Design-for-Test (DFT) architecture, implementation, and sign-off for complex flat SoC designs. This role requires deep expertise in PNR (Place-and-Route) within Cadence flow.

Key Responsibilities :

• Lead DFT strategy and implementation for flat SoC designs from RTL through tape-out.
• Develop and integrate test architectures including scan insertion, MBIST, LBIST, JTAG, and boundary scan.
• Work closely with the PNR team to ensure DFT structures are timing- and placement-aware.
• Drive test mode constraint creation and ensure compatibility with functional modes.
• Perform gate-level simulations for test logic verification.
• Own ATPG pattern generation and coverage analysis for manufacturing test.
• Lead reviews and mentor junior DFT engineers in best practices.

Qualifications : Must-Have :

Nice-to-Have :

(ref : hirist.tech)