Halma India - Design Verification Engineer - UVM / System Verilog

Job Description :

Key Responsibilities :

• Execute IP or subsystem verification of complex design blocks
• Develop verification plans, environments, and testbenches using SystemVerilog and UVM
• Perform functional verification and ensure robust coverage metrics
• Debug and resolve verification issues efficiently
• Collaborate with design teams for seamless integration and verification Skills :
• Proficiency in SystemVerilog (SV), UVM, assertions, and coverage-driven verification
• Strong experience in Fabric / NOC / Interconnect block verification
• Knowledge of AMBA suite protocols (AXI / ACE), PCIe, CXL, interrupt handling, and power to Have :
• Experience in coherent traffic Were Looking For :
• Strong problem-solving and debugging skills
• Excellent communication and teamwork abilities
• Ability to work independently and deliver high-quality verification

(ref : hirist.tech)