Design Verification Engineer - UVM / System Verilog

We are seeking a highly skilled and motivated Design Verification Engineer to join our hardware design team. The ideal candidate will have strong expertise in debug analysis, test planning, and verification methodologies to ensure high-quality deliverables. The role involves working on verification environments, debugging, and ensuring robust verification flows.

Key Responsibilities :

• Develop, implement, and execute verification plans to validate design specifications and requirements.
• Perform detailed debug analysis of simulation failures and identify root causes.
• Contribute to test plan creation, covering functional, performance, and power-related scenarios.
• Work with Power Artist verification environment to analyze and validate power optimization and efficiency.
• Perform environment flow cleanup, ensuring seamless and efficient verification workflows.
• Develop reusable verification components using standard methodologies.
• Collaborate with design, architecture, and implementation teams to ensure functional correctness.
• Track, document, and resolve verification issues to maintain project schedules and quality standards.
• Ensure compliance with verification methodologies, best practices, and industry standards.

Required Skills :

(ref : hirist.tech)