Senior Design Verification Engineer - UVM / System Verilog

About the Role :

Univision Technology Pvt Ltd is seeking an experienced and highly skilled Senior Verification Engineer to join our dynamic team. The ideal candidate will play a critical role in driving functional verification for Intellectual Properties (IPs) and System-on-Chip (SoC) designs. This position requires deep technical expertise in verification methodologies, protocols, and automation scripting to ensure the highest quality of design validation.

Key Responsibilities :

• Lead and drive the functional verification process for complex IPs and SoCs, ensuring thorough validation against specifications.
• Develop, implement, and maintain testbenches using SystemVerilog and the Universal Verification Methodology (UVM).
• Create and execute verification plans, test cases, and coverage models to maximize design validation.
• Perform verification of various serial and parallel communication protocols including MIPI, SPI, I2C, MDIO, UART, and high-speed SERDES interfaces.
• Utilize advanced verification techniques such as formal verification, gate-level simulation (GLS), and Unified Power Format (UPF)-based power simulations.
• Automate verification processes and data analysis using scripting languages, primarily Python.
• Collaborate closely with design engineers, architects, and other cross-functional teams to identify issues early and improve design

robustness.

Qualifications :

Preferred Skills :

(ref : hirist.tech)