Verification Engineer - UVM / System Verilog

Job Description :

• Define and implement verification strategies and test plans for DDR memory interface designs.
• Develop UVM / SystemVerilog-based testbenches and reusable verification components.
• Perform protocol-level verification for DDR memory interfaces and validate compliance.
• Collaborate with architecture, RTL, and system teams to understand design intent and corner cases.
• Own functional coverage, regression setup, and closure.
• Integrate DDR models, controllers, PHYs, and validate their interactions.
• Debug and resolve simulation failures and functional issues.
• Drive code and functional coverage improvements to ensure thorough verification.
• Lead or participate in technical reviews and mentor junior engineers.

Required Skills :

Preferred Qualifications :

(ref : hirist.tech)