MTS Silicon Design Engineer

PREFERRED EXPERIENCE :

• Proficient in IP level ASIC verification
• Proficient in debugging firmware and RTL code using simulation tools
• Proficient in using UVM testbenches and working in Linux and Windows environment s
• Experienced with Verilog, System Verilog, C, and C++
• Graphics pipeline knowledge
• Developing UVM based verification frameworks and testbenches, processes and flows
• Automating workflows in a distributed compute environment .
• Exposure to simulation profile, efficiency improvement, acceleration, HLS tools / process
• Strong background in the C++ language, preferably on Linux with exposure to Windows platform
• Good understanding and hands-on experience in the UVM concepts and SystemVerilog language
• Good working knowledge of SystemC and TLM with some related experience .
• Scripting language experience : Perl, Ruby, Makefile, shell preferred.
• Exposure to leadership or mentorship is an asset
• Desirable assets with prior exposure to video codec system or other multimedia solutions .

ACADEMIC CREDENTIALS :

• Bachelors or Masters degree in computer engineering / Electrical Engineering

Skills Required

Linux, Perl, Firmware, Digital Design, Mts, System Verilog