ACL Digital hiring for below position!
๐๐ฆ๐๐ ๐๐ฒ๐๐ถ๐ด๐ป ๐๐ป๐ด๐ถ๐ป๐ฒ๐ฒ๐ฟ
๐๐ผ๐ฏ ๐๐ฒ๐๐ฐ๐ฟ๐ถ๐ฝ๐๐ถ๐ผ๐ป
โช๏ธ Must have proven track record of ASIC design on several production tape-outs.
โช๏ธ Experience in Designing RTL block for an SOC.
โช๏ธ Experience in integrating ASIC IP into an SOC.
โช๏ธ Experience with Arm architecture and APB, AXI, CHI protocols.
โช๏ธ Experience with synthesis, static timing analysis & optimizations.
โช๏ธ Experience writing timing constraints and exceptions.
โช๏ธ Experience with automation using scripting techniques such as PERL, Python or Tcl.
โช๏ธ Ability to develop clear and concise engineering documentation.
โช๏ธ Ability to organize and present complex technical information.
โช๏ธ Strong verbal and written communication skills.
โช๏ธ Exhibit strong ownership of tasks and responsibilities.
๐๐ ๐ฝ๐ฒ๐ฟ๐ถ๐ฒ๐ป๐ฐ๐ฒ : ๐ฏ ๐๐ผ ๐ญ๐ฌ ๐ฌ๐ฒ๐ฎ๐ฟ๐
๐๐ผ๐ฐ๐ฎ๐๐ถ๐ผ๐ป : ๐๐๐ฑ๐ฒ๐ฟ๐ฎ๐ฏ๐ฎ๐ฑ
#asicdesign #socdesign #ipdesign #rtldesign #blockdesign #vlsijobs #jobshyderabad #vlsihyderabad #semiconhiring
Design Engineer โข hyderabad, telangana, in