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Design Engineer

Design Engineer

ACL Digitalhyderabad, telangana, in
30+ days ago
Job description

ACL Digital hiring for below position!

๐—”๐—ฆ๐—œ๐—– ๐——๐—ฒ๐˜€๐—ถ๐—ด๐—ป ๐—˜๐—ป๐—ด๐—ถ๐—ป๐—ฒ๐—ฒ๐—ฟ

๐—๐—ผ๐—ฏ ๐——๐—ฒ๐˜€๐—ฐ๐—ฟ๐—ถ๐—ฝ๐˜๐—ถ๐—ผ๐—ป

โ–ช๏ธ Must have proven track record of ASIC design on several production tape-outs.

โ–ช๏ธ Experience in Designing RTL block for an SOC.

โ–ช๏ธ Experience in integrating ASIC IP into an SOC.

โ–ช๏ธ Experience with Arm architecture and APB, AXI, CHI protocols.

โ–ช๏ธ Experience with synthesis, static timing analysis & optimizations.

โ–ช๏ธ Experience writing timing constraints and exceptions.

โ–ช๏ธ Experience with automation using scripting techniques such as PERL, Python or Tcl.

โ–ช๏ธ Ability to develop clear and concise engineering documentation.

โ–ช๏ธ Ability to organize and present complex technical information.

โ–ช๏ธ Strong verbal and written communication skills.

โ–ช๏ธ Exhibit strong ownership of tasks and responsibilities.

๐—˜๐˜…๐—ฝ๐—ฒ๐—ฟ๐—ถ๐—ฒ๐—ป๐—ฐ๐—ฒ : ๐Ÿฏ ๐˜๐—ผ ๐Ÿญ๐Ÿฌ ๐—ฌ๐—ฒ๐—ฎ๐—ฟ๐˜€

๐—Ÿ๐—ผ๐—ฐ๐—ฎ๐˜๐—ถ๐—ผ๐—ป : ๐—›๐˜†๐—ฑ๐—ฒ๐—ฟ๐—ฎ๐—ฏ๐—ฎ๐—ฑ

#asicdesign #socdesign #ipdesign #rtldesign #blockdesign #vlsijobs #jobshyderabad #vlsihyderabad #semiconhiring

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Design Engineer โ€ข hyderabad, telangana, in