RTL Design Engineer- High Speed IP

You are a highly motivated and experienced ASIC Digital Design Engineer with a strong background in digital design for high-speed serial interfaces .

You have a deep understanding of USB, PCIe, Ethernet, Display, and HDMI protocol standards , and you thrive in a collaborative environment.

Your expertise in Verilog RTL design, microarchitecture, and timing constraints development makes you a valuable asset to any team. You are adept at using tools like Spyglass for CDC / RDC / Lint and have excellent debugging skills.

Your ability to propose and implement design updates based on various requirements, coupled with your experience in test coverage and physical design timing closure , sets you apart as a leader in your field.

With a passion for innovation and a keen eye for detail, you are ready to take on new challenges and contribute to the success of Synopsys.

What You'll Be Doing :

• Driving and working on digital design for high-speed serial interface PHY IPs for USBx, PCIex, Ethernet, Display, and HDMI protocol standards.
• Proposing micro-architecture of design / design updates based on customer requirements, analog requirements, system performance improvements, Link layer interface changes, or overall robustness of design.
• Implementing RTL in Verilog and running Spyglass CDC / RDC / Lint.
• Collaborating with verification teams to test desired functionality and corner cases.
• Developing timing constraints, DFT insertion, and test coverage , and closing timing with physical design teams.
• Well versed in Micro-Architecture and Block Ownership, Design from scratch.

The Impact You Will Have :

What You'll Need :

Who You Are :

Skills Required

Asic, Dft, Verilog, Ethernet, Perl, Rtl Design