Sr Staff Verification Engineer – SoC / IP Design Verification

Job Description

We are seeking a Senior Staff Verification Engineer to lead and contribute to the functional verification of complex SoC and IP designs for next-generation AI, HPC, and data center products. The ideal candidate has extensive experience in UVM / SystemVerilog , SoC and IP-level verification, and is passionate about ensuring first-pass silicon success .

This role involves defining verification strategies, developing scalable environments, and collaborating cross-functionally with architecture, design, and software teams. Experience with Virtual Modeling, SystemC, and TLM is a plus , enabling advanced verification and early system-level validation.

Qualifications

Required Qualifications

• Education & Experience B.S. / M.S. in Electrical Engineering, Computer Engineering, or related field. 8+ years of experience in IP / SoC verification with a proven track record of successful silicon delivery.
• Technical Expertise Deep knowledge of UVM / SystemVerilog for testbench development and verification IP integration.Strong understanding of SoC architecture and protocols such as DDR5, HBM3, PCIe Gen6, CXL 3.0 , and other high-speed interfaces.Expertise in coverage-driven verification , constrained-random testing, and assertion-based verification.Proficient in debugging RTL, testbenches, and simulation failures using industry-standard tools.
• Tools & Languages Hands-on experience with simulation tools (VCS, Xcelium, Questa, etc.), waveform viewers, coverage tools, and automation scripting (Python, Perl, TCL).

Preferred / Additional Skills