Job Description :
The position involves design verification of next generation IPs / SoCs with emphasis on verifying and signing off performance and power along with functionality by developing the needed RNM models . This role will require the candidate to understand and work on all aspects of VLSI Verification cycle like Testbench architecture, Verification Planning, Testbench and Test development, Verification closure with best-in-class methodologies including simulation, GLS . Candidate will require close interactions with Design, SoC , Validation, Synthesis & PD teams for design convergence. Candidate must be able to take ownership of IP / Block / SS :
- To work in AMS Verification domain with relevant experience in mixed signal SOCs or subsystems / IPs.
- Leading a project for AMS requirements is a value add.
- Proficiency in AMS simulation environment using Cadence / Synopsys / Mentor tools. Knowledge of digital design techniques, Verilog HDL, and standard RTL coding styles, as well as analog circuit basics, with previous analog design experience a plus.
- Candidate should be familiar with the concepts of behavioral modeling both digital (Verilog-D) and analog (Verilog-A or Verilog-AMS).
- Experience in SV and UVM testbench development / modifications from mixed signal perspective is a plus.
- Functional knowledge of analog and mixed signal building blocks, such as comparators, op-amps, switched cap circuits, various types of ADCs and DACs, current mirrors, charge pumps, and regulators is expected.
- Experience working on AMS Verification on multiple SOCs or sub-systems.
- Working knowledge of Perl / Skill / Python / Tcl or other scripting relevant language is a plus.
- Candidate should have ability to lead a project team, and work collaboratively in a multi-site development environment.
- Delivery oriented, Passionate to learn and explore, Transparent in communication, Flexibility related to project situations.
- Candidates should have a good knowledge of analog and mixed signal electronics, test-plan development, tools and flows.
- Develop and execute top-level test cases, self-checking test benches and regressions suites.
- Developing and validating high-performance behavior models.
- Verifying of block-level and chip-level functionality and performance.
- Team player with good communication skills and previous experience in delivering solutions for a multi-national client.
Tool suites :
Predominantly analog (Cadence Virtuoso).SPICE simulator experience.Fluent with Cadence-based flowCreate schematics, Simulator / Netlist options etc.Ability to extract simulation results, capture in a document and present to the team for peer review.Supporting silicon evaluation and comparing measurement results with simulations.UVM and assertion knowledge would be an Level : 5 to 15 years (with strong hands-on AMS Verification expertise; 712 years preferred), WorkLocation : Hyderabad , Requirements : Bachelor or Masters degree in Electrical and / or Computer Qualifications :
Proficient in at least one of the following languages : Verilog, SystemVerilog, VerilogAMS.Strong understanding of analog circuits, digital design processes, and top-level integration.Basic knowledge of PMIC and DC-DC converters.Excellent simulation debugging skills, with the ability to analyze waveforms and identify issues in schematics, models, or RTL.Proficient in Unix environment and shell scripting, with a basic understanding of Python.(ref : hirist.tech)