Senior Design Verification Engineer

Senior Design Verification Engineer

Experience : 5-10 years

Location : Hyderabad

Functional Verification Engineer

Role Summary :

We are seeking an experienced Functional Verification Engineer with strong expertise in SystemVerilog / UVM to develop and maintain verification environments for block-level and IP-level designs. The ideal candidate will be proactive, self-driven, and capable of managing deliverables independently.

Key Responsibilities :

• Develop and maintain block-level testbenches using SystemVerilog / UVM.
• Create and execute verification plans (Vplan), run regressions, and achieve coverage closure.
• Work on testbenches with real number modeling.
• Perform netlist and gate-level simulations.

Qualifications & Experience :

Interested,please share your updated resume to janagaradha.n@acldigital.com