Implementing digital blocks using state-of-the-art gate to GDSII ASIC flows.Performing physical implementation of blocks from gate netlist to GDSII.Conducting signoff verifications, including layout verifications (DRC, LVS, Antenna) and reliability verifications (EMIR, ESD).Writing MCMM and UPF for block designs.Providing handoff data for other signoff closure processes like STA, formality, layout, and reliability verification.Collaborating with cross-functional teams to ensure the successful integration and testing of physical designs.The Impact You Will Have :
- Enhancing the quality and reliability of our digital block implementations.
- Driving innovation in physical design methodologies and processes.
- Enabling the successful deployment of high-performance silicon chips.
- Contributing to the development of cutting-edge technology that powers next-generation applications.
- Supporting the continuous improvement of our ASIC design flow and tools.
- Ensuring the seamless integration of physical designs into larger systems and platforms.
What You 'll Need :
- In-depth understanding of the ASIC physical design flow steps from gate netlist.
- Experience in testchip implementation and testing exposure is a plus.
- Exposure to Synopsys toolset (such as FC / ICC2, Primetime, Formality, ICV) is highly desirable.
- Experience with FinFET designs is desirable.
- Experience in working on IO integration with wire-bond or flip-chip design is a big plus.
Skills Required
Asic, Semiconductor, Chip Design, Circuit Designing, silicon, Physical Design