ASIC Digital Design, Sr Engineer

The Impact You Will Have :

• Contributing to the development of cutting-edge SerDes products that lead the industry.
• Enhancing the performance, power, and size efficiency of our silicon IP offerings.
• Enabling rapid market entry for differentiated products with reduced risk.
• Driving innovation in high-speed digital design and data recovery circuits.
• Supporting the creation of high-performance silicon chips and software content.
• Collaborating with a world-class team to solve complex design challenges.

What You ll Need :

• BSEE or MSEE with a minimum of 2 years of experience in digital design and front-end flows.
• Proficiency in running lint / cdc / rdc checks and synthesis flow.
• Experience in coding, verifying Verilog and System Verilog design.
• Experience of working with minimum supervision and owning and delivering for front-end activities in IP / SOC.
• Experience of leading technically for front-end activities.
• Knowledge of digital design methodologies, DFT insertion, synthesis constraints, and flows.
• Scripting experience in Shell, Perl, Python, and TCL (preferred).

Who You Are :

• Excellent communicator with the ability to interact with diverse teams.
• Self-motivated and proactive, with a strong attention to detail.
• A creative problem-solver who can think independently.
• Capable of working under tight deadlines while maintaining high-quality standards.
• A team player who can contribute effectively both individually and collaboratively

Skills Required

Digital design and front-end flows, Verilog / SystemVerilog coding and verification, Lint / CDC / RDC checks (VC-Spyglass), Synthesis (Design Compiler / Fusion Compiler), Static Timing Analysis (STA)