Formal Verification Engineer

About Iravan

Iravan Technologies, headquartered in Pune, is a semiconductor design services company specializing in Mixed-Signal, Digital, and Formal Verification. We partner with leading companies across Storage, Networking, Aerospace, Automotive, Defense, and other critical industries to deliver advanced semiconductor solutions.

Designation : Formal Verification Engineer

Experience : 4+ Relevant in FV

Location : BLR / Pune

Vacancies : 02

JD

Experience with Formal Verification (e.g., sequential equivalence checking, Security Path verification, connectivity, low power and Formal property verification).

Experience with programming languages (e.g., Python / Perl and TCL).

Experience with at least one formal verification tool (e.g., Cadence Jasper, Synopsys VC-Formal).

Expertise in property specification languages (e.g., SVA, PSL), as well as proficiency in HDLs such as System Verilog, Verilog or VHDL.

Interested candidates may share resumes at [HIDDEN TEXT] - (Immediate to 30-day notice period candidates preferred)

Skills Required

Cadence, Jasper, Vhdl, formal verification, Perl, Verilog, System Verilog, SVA, Python, Tcl