Principal CPU Design Verification Engineer - System Verilog / UVM

Principal CPU Design Verification Engineer

We are seeking an experienced verification engineer to lead verification efforts of complex CPU and related subsystems based on the open-source RISC-V architecture. The right candidate will have deep technical expertise combined with exceptional leadership skills.

Responsibilities :

• Lead end-to-end verification from complex CPU sub-units up to CPU clusters, partnering with architecture and design teams
• Develop verification infrastructure components including test-benches, scoreboards, and stimulus generators
• Develop and execute comprehensive verification plans for units and features
• Implement functional coverage models
• Debug designs in simulation, prototyping platforms, and silicon
• Continuously drive methodology improvements to improve efficiency
• Lead senior and junior engineers as a team to accomplish successful projects

Minimum Qualifications :

Skills & Qualifications Required :

(ref : hirist.tech)