RTL / Soc Design & Integration Lead

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MTS SILICON DESIGN ENGINEER

The Role

The focus of this role in the AECG ASIC organization is to provide hands-on technical leadership in developing microarchitecture, implementing the design in RTL, RTL Integration etc. ensuring quality (design checks and verification reviews) and PD support for next generation ASICs

The Person

You have a passion for modern, complex SoC architecture with various IO peripherals and heterogeneous processor systems and digital design & verification in general. You are a team player who has excellent communication skills and experience collaborating in a corporate environment with other architects & engineers located in different sites / time-zones. You have strong analytical and problem-solving skills and are willing to learn and ready to take on problems.

Key Responsibilities

• Define and specify micro-architecture of ASIC building blocks and necessary infrastructure based on architecture, PPA, DFT, Functional Safety requirements
• RTL design and debug of complex blocks in Verilog / System Verilog
• Analyze design metrics and make implementation choices to optimize PPA
• RTL Integration
• Work with implementation, verification and physical design teams to achieve high quality design and successful tape out
• Address customer problems through innovative enhancements to product architecture / micro-architecture
• Collaborate with cross-functional teams to solve novel problems across multiple functional areas in development of clocking features and / or algorithms
• Lead internal and external teams for RTL design

Preferred Experience

Academic Credentials

Benefits offered are described : AMD benefits at a glance.

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and / or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants' needs under the respective laws throughout all stages of the recruitment and selection process.

Skills Required

Soc Architecture, Linux Environment, Rtl Design, Python Scripting, spyglass, Digital Design, Version Control Systems, Perl, Verilog, System Verilog, Tcl