RTL Design Integration Lint / CDC

RTL Design Integration Lint / CDC

3-10 Yrs Exp

Notice Period : Immediate to 1 Month

BLR / Hyd locations

Experience with micro architecture design and system design. Using Verilog, SV or VHDL.

Strong background in RTL design Verilog, System Verilog

• Experience in Spyglass Lint, CDC, SoC Integration
• Experience in Logic design with Verilog, SV
• Experience in ASIC Synthesis, STA and timing closure
• Experience in any Processor based system, design with SoC, AXI / AHB / APB System bus and peripherals Ethernet, PCIe, DDR , USB, UART, SPI , I2C etc
• Synthesis, Timing Analysis through various industry standard tools.

Developed complex SOC and IP modules

Proficient in defining SOC architecture, High level design document, Low level design document, Code reviews