Staff Verification Engineer

Job description

Hiring : Staff Verification engineers

ExperienceLevel : 7+Years

Job Location : Hyderabad

Role Description

The position involves designing, developing and deploying UVM based reusable testbenches for RTL unit blocks, sub-system level and top level systems with emphasis on

verifying the functionality and generating the code / functional coverage reports. The candidate should come up with test plans and test cases in order to achieve 100% code coverage and functional coverage.

Qualifications

• Experience in ASIC / FPGA verification using System Verilog.
• Develop and sign off on test plans and test cases.
• Strong knowledge of digital design, Verilog, System Verilog, UVM, C / C++.
• Experience in AMBA AHB / AXI / APB based IPs design / verification.
• Experience in usage of assertions, constrained random generation, functional and code coverages
• Formal Verification and Functional Verification skills
• RTL Design and Computer Architecture skills
• Debugging skills
• Bachelor&aposs or Master&aposs degree in Electrical Engineering or related field

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Skills Required

Computer Architecture, Debugging, Uvm, code coverage , AMBA, Axi, formal verification, APB, Verilog, Functional Verification, AHB, System Verilog, Rtl Design