Design Engineer I

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

• BE / BTECH 1-4 yrs
• Very good knowledge on SCAN / ATPG / JTAG / MBIST
• Experience with one or more chip tape out that includes chip ATE bring up.
• Experience on gate level simulation with no timing and timing (SDF) simulations (ATPG / MBIST / JTAG)
• Experience in Test structures for DFT, IP integration, ATPG fault models, test point insertion, coverage improvement techniques.
• Experience in scan insertion techniques at block level and chip top level.
• Experience on Memory BIST generation, insertion, verification on RTL / Netlist level.
• Good knowledge and understanding in Analog PHY and Analog Macro tests.
• Good knowledge and understanding on JTAG for IEEE 1149.1 / IEEE1149.6 standards.
• Good knowledge on test mode timing constraints
• Good knowledge about running block level and chip STA flows.
• Cross domain knowledge to resolve DFT issues with design, synthesis, physical design, STA team.
• Proficiency in industry standard tools for scan insertion, ATPG, MBIST and JTAG (preferable Cadence / Tessent tools)
• Experience with post-silicon bring up and debug on ATE.
• Good knowledge on Perl / Tcl scription skills
• Very good team player capabilities and excellent communication skills to work with a variety of teams across the global organization.
• High sense of responsibility and ownership within the team for successful tape out and post-silicon bring up of project.

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