Senior Engineer II - Software Design

Are you looking for a unique opportunity to be a part of something great Want to join a 17,000-member team that works on the technology that powers the world around us Looking for an atmosphere of trust, empowerment, respect, diversity, and communication How about an opportunity to own a piece of a multi-billion dollar (with a B!) global organization We offer all that and more at Microchip Technology, Inc.

People come to work at Microchip because we help design the technology that runs the world. They stay because our culture supports their growth and stability. They are challenged and driven by an incredible array of products and solutions with unlimited career potential. Microchip's nationally-recognized Leadership Passage Programs support career growth where we proudly enroll over a thousand people annually. We take pride in our commitment to employee development, values-based decision making, and strong sense of community, driven by our we affectionately refer to it as the and it's won us countless awards for diversity and workplace excellence.

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Job Description :

This position is an excellent opportunity for someone willing to work on making himself / herself a domain expert & mastering in EDA

SW development with touch of FPGA HW. The individual will work on deeply understanding Silicon / FPGA architecture and inside

complex IPs / core blocks and bring a tcl based core to configure the block functionality. Few complex cores will have C++ based UI

developement. The individual must have strong knowldage & expereience on various FPGA IPs / Cores, protocols and memories and

should interact with stake holders to conclude on configuration options in UI. In addition, the individual must be able to work in a

fast-paced, high-demand, multiple-deadline driven environment.

Job Location : Hyderabad, Telangana, India

Responsibilities

• Read and understand the Silicon Architecture specifications.
• Define macros / primitves and guide and / or develop the software core to configure IP blocks in Microchip FPGAs like SERDES, Etherent, PCIe, PLL and Memories (DDR, RAMs and uPROM) involving tcl based core development, UI development and Netlist generation.
• A tcl based core development to generate Verilog netlist to connect various macros / primitves. Few complex cores will involve UI development using C++ and Qt frameworks.
• Generation of design files (netlist, register settings, timing constraints files) for various hard IP blocks in Microchip FPGAs.
• Should be able to capture the requirements and create Software requirements document.
• Should be able to create simple designs to test the Synthesis & PnR flow for generated netlist.
• Should be able to estimate the efforts and provide the plan for completing the requirements.
• Propose / review test plans
• Work across with multiple teams in accomplishing the tasks.
• Assist and train Juniors engineers
• Debugging and Bug fixing

Requirements / Qualifications :

Education

Required Skills

Skills Required

Gpio, SDRAM, Spi, Qt, Usb, Verilog, Tcl, AHB, I2c, DMA, Ethernet, Python, Pcie, Perl, Axi, Ddr