Lead DFT Engineer (13 / 10 / 2025)

DFT resource with 8+ yrs experience.

• Strong background and experience with Scan design, Clock architecture, ATPG methodology and industry standard tools
• Worked on Test compressions and decompression scan methodology generating test patterns at block and SoC level.
• Worked on ATPG test pattern generation stuck-at and at-speed with depth fault coverage analysis identifying issues to meet the coverage targets.
• Worked on boundary Scan test plan, test coverage with JTAG
• Understand MBIST concepts and insertion and test the integration at partition and SoC level.
• Understand the concept of memory redundancy logic.
• Understand JTAG concepts with all jtag IEEE standards
• Worked on industry standard DFT tools
• Strong knowledge on scripting in TCL / Perl / Python.
• Must possess good communication skills, be a self-driven individual and a good team player

Interested can apply karthick.v@acldigital.com