Senior DFT Engineer

Change the world. Love your job.

TI offers one of the world's largest portfolio of power management and delivery for CPU and GPU Servers, personal electronics and automotive. Our team has full product development responsibility from definition till releasing products to market for enterprise power delivery. We take pride in pushing the boundaries on innovation & executing ideas into winning products. Our team spans the entire spectrum of Systems and IP Specifications, System Level Simulations, Micro-Architecture Definition, Low Power Low Latency Architectures, IP Development, Advanced DFT, Formal Verification, Physical Design, Test, Validation and Application Engineering. We have a strong system that fosters technical innovations, publications and knowledge sharing. Our people-centric approach encourages collaboration, mentoring, multiskilling, domain rotation and ownership leading to accelerated career growth and an engaging working environment.

We are now looking for talented Design for Test engineers for multi-million gate controller ASICs.

Minimum Requirement

3-5 years

of relevant industry experience of which 2+ yr should be in chip / IP level DFT implementation.

JTAG protocol basics.

Understanding of DFT & ATPG concepts & best practices : Clock gating / bypass, Reset Bypass, Scan Collar, Clock Shaping, Fault models, Pattern Generation, Coverage, Debug and Closure of Coverage Gaps.

Hands on experience in synthesis and scan stitching, scan chain integrity checks and test point insertion, scan architectures, clock generation architecture for at-speed tests with industry tools in a must. Cadence toolchain is preferred (Modus, Genus, Xcelium)

Scripting in Tcl, Python / Perl / C

Strong analytical and debugging skills

Bachelor's degree in Electrical / Electronic Engineering or related field

Thorough understanding of digital logic design with Verilog / System Verilog

Preferred Qualifications

Experience in full-chip level DFT implementation

Memory testing concepts : basics of memory testing algorithms, test architectures.

Experience in ATE debug will be a plus

LEC constraining for DFT.

STA concept, DFT for multiple clock domains

Debugging of mis-compares during pattern simulation.

Experience in IP design and / or verification would be a plus

Master’s degree in Electrical / Electronic Engineering or related field