Job Description-
The candidate is expected to have clear understanding of IJTAG, P1500 protocols and should have hands on experience of at least one of these.
The candidate is expected to have clear understanding of BSCAN,MBIST, SCAN, ATPG and Simulation concepts.
Must be hands-on with MBIST insertion, Scan Insertion, ATPG pattern generation and simulations, MBIST and BSCAN simulations using industry standard tools of Cadence / Siemens Tessent / Synopsys.
He / she must have worked on zero delay as well as SDF Timing Simulations.
Must have good debugging skills using GUI mode of industry standard simulators like VCS, NCSim or Xcelium.
The candidate should have worked on fault models like stuck-at, Transition Delay Faults(TDF), IDDQ and should have experience in scan test coverage improvement techniques.
He / she should have worked in SoC level DFT with experience in OCC / OPCG insertion, EDT / Compression logic insertion, clock module handling for scan purposes and post-silicon bring-up and / or production activities with exposure to Tester debug usings shmoo plots and graphs.
The candidate should have experience of providing test mode timing constraints to STA and PD teams.
Additional knowledge of perl / tcl scripting will be an advantage.
Good communication skills and debugging skills are a must to have qualities for this role as it involves cross-functional teams and customer teams communications along with internal DFT team leading and mentoring of DFT Engineers.
Good to have skills - DFT architecture and implementation knowledge of chiplet based implementations
Exp- 5+ years
About Company :
7Rays Semiconductors Private Ltd. is a provider of end to end custom SoC design solutions ranging from SoC Architecture, RTL design, Design verification, DFT, Physical Design & Analog design. We are focused on providing services to top semiconductor and system companies to help them with the design of their complex SoCs
Lead Engineer • India