Lead IP Design Engineer
Mulya TechnologiesHyderabad, Republic Of India, IN30+ days ago
Job descriptionEducation : BS / MS / PhD in Electronics / Computer Engineering. Experience : 10+ years in ASIC / FPGA IP / RTL design, 5+ years with ARM Neoverse and CMN fabrics (e.G., CMN-600 / 700 / S3). Skills : Expert in Verilog / SystemVerilog RTL design. Deep knowledge of ARM Neoverse (V1 / V3 / N2 / N3) and CMN interconnects. Deep understanding in system architecture, coherence and cache Experience with Arm Socrates for CMN configuration. Proficiency in AMBA CHI, CXL, PCIe, or CCIX protocols. Familiarity with synthesis and timing tools (e.G., Synopsys Design Compiler). Experience with AI / HPC or datacenter SoC design. Knowledge of DDR5, HBM3, or chiplet-based architectures. Familiarity with UALink or Ultra Ethernet. Strong problem-solving and collaboration skills. Pure play product work environment Chance to work with a tightly knit group of exceptional engineers who come from the top companies of the Semiconductor world Our pay comprehensively beats "ALL" Semiconductor product players in the Indian market. A meritocracy first work place where each peer is a star A chance to be a part of industry shaping product in entirety (not bits and pieces) from initial stages A chance to work at a startup which already has customers and investor lined up for their product pipeline (We do not have a marketing / sales team, because we do not need them). A chance to learn from industry veterans who have already launched multiple Billion Dollar Semiconductor firms over the last 3 decades.
Principal IP / RTL Design Engineer for ARM CMN Fabric and Neoverse
Hyderabad / Bangalore
Founded by highly respected Silicon Valley veterans - with its design centers established in Santa Clara, California. / Hyderabad / Bangalore
Our pay comprehensively beats "ALL" Semiconductor product players in the Indian market.
IP / RTL Design Engineer for ARM CMN Fabric and Neoverse
Position Overview
Seeking an IP / RTL Design Engineer with 10+ years of experience to design IP / RTL for ARM Neoverse-based SoCs, focusing on CMN fabric, using Socrates for configuration, targeting AI / HPC datacenter applications.
Key Responsibilities
- Design IP blocks for ARM Neoverse SoCs, integrating CMN fabric (e.G., CMN-700 / S3) for cache coherence and interconnect.
- Develop Verilog / SystemVerilog RTL for high-performance, low-latency designs.
- Configure CMN topologies using Arm Socrates for optimized performance and scalability.
- Implement protocols like AMBA CHI, ACE, CXL, PCIe for coherent interconnects.
- Optimize designs for bandwidth, latency, and power in AI / HPC workloads.
- Support synthesis, timing closure, and FPGA prototyping and Design Verification team
- Document microarchitecture and design specifications.
Required Qualifications
What is in it for you?
Contact : Uday
Mulya Technologies
muday_bhaskar@yahoo.com
"Mining The Knowledge Community"
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Lead Design Engineer • Hyderabad, Republic Of India, IN
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