Principal IP / RTL Design Engineer for ARM CMN Fabric and Neoverse

Principal IP / RTL Design Engineer for ARM CMN Fabric and Neoverse

Hyderabad / Bangalore

Founded by highly respected Silicon Valley veterans - with its design centers established in Santa Clara, California. / Hyderabad / Bangalore

Our pay comprehensively beats "ALL" Semiconductor product players in the Indian market.

IP / RTL Design Engineer for ARM CMN Fabric and Neoverse

Position Overview

Seeking an IP / RTL Design Engineer with 10+ years of experience to design IP / RTL for ARM Neoverse-based SoCs, focusing on CMN fabric, using Socrates for configuration, targeting AI / HPC datacenter applications.

Key Responsibilities

• Design IP blocks for ARM Neoverse SoCs, integrating CMN fabric (e.g., CMN-700 / S3) for cache coherence and interconnect.
• Develop Verilog / SystemVerilog RTL for high-performance, low-latency designs.
• Configure CMN topologies using Arm Socrates for optimized performance and scalability.
• Implement protocols like AMBA CHI, ACE, CXL, PCIe for coherent interconnects.
• Optimize designs for bandwidth, latency, and power in AI / HPC workloads.
• Support synthesis, timing closure, and FPGA prototyping and Design Verification team
• Document microarchitecture and design specifications.

Required Qualifications

What is in it for you?

Contact : Uday

Mulya Technologies

muday_bhaskar@yahoo.com

"Mining The Knowledge Community"