KEY RESPONSIBILITIES :
- Work as a member of a geographically distributed verification team to verify next-generation ASIC and FPGAs
- Develop testplans, implement testbenches, create testcases, and ensure functional coverage closure
- Handle regression testing and contribute to verification infrastructure development
- Develop both directed and random verification tests
- Debug test failures, identify root causes, and work with RTL and firmware engineers to resolve design defects and test issues
- Review functional and code coverage metrics, modify or add tests or constrain random tests to meet coverage requirement
- Collaborate with design, software and architecture teams to verify design under test
PREFERRED EXPERIENCE :
Proficient in IP-level FPGA and ASIC verificationKnowledge of PCIe, CXL or other IO protocol is preferredProficient in Verilog / SystemVerilog, and scripting languages such as Perl or PythonHands-on experience with SystemVerilog and UVM is mandatoryExperience in developing UVM-based verification testbenches, processes, and flowsSolid understanding of design flow, verification methodology, and general computational logic design and verificationTHE ROLE :
As a Silicon Design Engineer, you will work with formal experts and designers to verify formal properties and drive convergence .
ACADEMIC CREDENTIALS :
Bachelor s or M aster s degree in computer engineering / Electrical Engineering with 4+Yrs of expSkills Required
Python, Perl, Pcie, Asic verification, Testing