Staff SerDes Analog Design
Milpitas / Austin / Bangalore / Fort Collins / Billerica / Hyderabad
Hybrid
www.omnidesigntech.com
Omni Design Technologies is at the forefront of Wideband Signal Processing™ delivering high-performance, low-power analog-to-digital converters (ADCs), digital-to-analog converters (DACs), and other mixed-signal IP cores. These components are crucial for a wide array of modern applications, including artificial intelligence (AI) infrastructure, advanced wireless communications like :
- 5G networks and optical communications
- Automotive networking, LiDAR, and radar systems
- SatComm, Software Defined Radio (SDR) and other broadband communications
SerDes analog designer focusing 100Gbps+ wireline technologies (TX and RX path). The successful candidate in this role will develop cutting-edge circuits and architectures for ultra-high speed wireline communication systems, and will drive the development of high performance transistor level design starting from initial specification, through design and layout supervision, silicon evaluation and characterization to final product introduction to market.
Qualifications
6+ years of experience in high-performance analog or mixed-signal IC development in advanced CMOS processesFamiliarity with high-speed analog design and building block circuits for SERDES technology such as ADC / DAC, CTLE, CDR, PLL etc.Must have a track record of successfully taking designs to productionAbility to work with customers to define products that address needsMust have experience with evaluating silicon on bench and familiarity with standard lab equipmentStrong intuitive and analytical understanding of transistor-level circuit design including noise and mismatch analysisExperience with analog and digital behavioral modeling, and / or synthesis of digital control blocksFamiliar with Cadence schematic capture, virtuoso, Spectre and / or HSPICE circuit simulation toolsMATLAB understanding would be preferred but not mandatoryFamiliar with designing circuits for electromigration and ESD compliance in submicron CMOS processMust be familiar with layout parasitic extraction tools and layout dependent impairments in advanced CMOS processesMust be able to work independently, create and adhere to schedulesMust possess strong written and verbal communication skills with an ability to work with teams spread across geographic locationsContact : Uday
Mulya Technologies
muday_bhaskar@yahoo.com
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