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Lead Analog Design Engineer

Lead Analog Design Engineer

ConfidentialHyderabad / Secunderabad, Telangana
30+ days ago
Job description
  • Design and develop analog / mixed-signal blocks for PCIe 6 and PCIe 7 PHY designs.
  • Ensure designs meet PCIe protocol standards, optimizing for performance, power, and area targets.
  • Support the porting of PHY designs to different technology nodes, maintaining signal integrity and performance.
  • Collaborate with cross-functional teams to integrate analog circuits into larger SerDes PHY systems.
  • Implement verification strategies for high-speed analog / mixed-signal circuits using advanced simulation tools.
  • Work closely with physical layout teams to minimize parasitics, device stress, and process variation impacts.
  • Analyze simulation and measurement data for design validation and compliance with PCIe standards.
  • Provide technical guidance to junior engineers in analog / mixed-signal design methods.
  • Document design features, specifications, and test plans for future reference.
  • Work with the characterization team to validate the electrical performance of circuits in silicon.
  • The Impact You Will Have : Drive the development of cutting-edge PCIe 6 and PCIe 7 PHY designs, pushing the boundaries of high-speed analog and mixed-signal circuits.
  • Ensure that Synopsys designs meet the highest standards of performance, power efficiency, and area optimization.
  • Enhance the reliability and integrity of our analog circuits as they are ported to new technology nodes.
  • Foster innovation through collaboration with diverse teams, integrating leading-edge analog circuits into sophisticated SerDes PHY systems.
  • Contribute to the verification and validation of high-speed circuits, ensuring compliance with stringent PCIe standards.
  • Mentor and guide junior engineers, nurturing the next generation of top-tier analog designers.
  • What You ll Need : PhD with 3+ years, or MTech / MS with 8+ years of experience in analog / mixed-signal circuit design, with experience in high-speed interfaces such as PCIe or SerDes PHY designs.
  • Strong experience in transistor-level design of high-speed analog building blocks, such as LDOs, Bandgap references, ADC / DAC, PLLs, DLLs.
  • Experience in high-speed SerDes AFE (Analog Front-End) development, including CTLE and CDR design.
  • Experience designing high-speed SerDes transmitters, with knowledge of equalization techniques (e.g., DFE, FIR filters, TX pre-emphasis).
  • Understanding of jitter budgeting analysis, including sources of jitter and strategies for minimizing its impact.
  • Strong knowledge of CMOS technologies, including finFET and GAA processes.
  • Good understanding of the PCIe protocol, signal integrity requirements, and high-speed clocking.
  • Ability to provide input on layout design to minimize the effects of parasitics and process variations.
  • Who You Are : Detail-oriented with a passion for innovation and excellence.
  • Proactive and able to work independently with limited supervision.
  • Strong communicator capable of effectively collaborating with cross-functional teams.
  • Mentor and leader, eager to share knowledge and help develop junior engineers.
  • Results-driven with a focus on delivering high-quality, reliable designs

    • Skills Required

    Linux Environment, Algorithm Development

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    Lead Design Engineer • Hyderabad / Secunderabad, Telangana