Analog Design, Sr Manager

Responsibilities :

• Manage and mentor a team of 8-10 senior analog designers focused on high-speed SerDes IP development across multiple projects
• Define architecture specifications and circuit implementation requirements for next-generation SerDes PHY IPs
• Ensure adherence to project schedules, quality metrics, power / area targets through effective team oversight
• Collaborate with cross-functional teams (digital design, physical design, CAD) to integrate analog IP components
• Partner with process engineering teams to enable robust analog IP across advanced FinFET nodes
• Continuously drive design methodology improvements and adoption of latest EDA tools / flows
• Develop and manage operational plan, including staffing, budgets and resource allocation
• Hire, develop and retain top analog engineering talent through active mentorship

Requirements :

Skills Required

SerDes architecture and design, High-speed I / O circuit design, CDR / DFE / CTLE / EQ techniques, Analog / mixed-signal IC design, FinFET technology