Radiant Semiconductors - Design Verification Engineer - UVM / System Verilog

Description : Design Verification Engineer

Location : Bengaluru

Experience : 4 to 15 Years

Job Description :

We are hiring Design Verification Engineers with expertise in functional verification of complex IPs and subsystems.

The ideal candidate should have strong UVM knowledge and experience across high-speed protocols.

Key Responsibilities :

• Write functional coverage models based on DV plans
• Develop assertions and scoreboard-based checkers
• Analyze digital and functional coverage metrics
• Develop UVCs and UVM tests to close coverage gaps
• Work on protocols such as PCIe, UCIe, Ethernet, DDR, AMBA, and CPU
• Debug and close regressions effectively

Skills :

(ref : hirist.tech)