Design Verification Engineer

We are seeking a skilled and motivated Design Verification Engineer (DV) with expertise in Ethernet protocols, MAC layer functionality, and RoCE (RDMA over Converged Ethernet). The ideal candidate will have hands-on experience with Synopsys Ethernet PHY and controller IPs , and a strong understanding of high-performance networking technologies.

Key Responsibilities

Develop and execute verification plans for Ethernet MAC and PHY IP blocks

Design and implement testbenches using industry-standard methodologies (UVM, SystemVerilog)

Validate RoCE protocol implementations for low-latency, high-throughput data transfer

Collaborate with design and architecture teams to ensure functional correctness and performance

Debug and resolve issues across simulation and emulation platforms

Contribute to coverage analysis and closure

Preferred Qualifications

Strong knowledge of Ethernet protocols , including MAC layer operations

Experience with RoCE (RDMA over Converged Ethernet) and its application in high-speed networking

Familiarity with Synopsys Ethernet PHY and controller IPs

Proficiency in SystemVerilog , UVM , and simulation tools (VCS, Questa, etc.)

Background in ASIC / FPGA design and verification

Excellent problem-solving and communication skills

Bonus Skills

Exposure to high-performance computing or data center architectures

Experience with formal verification or emulation platforms

Knowledge of PCIe, TCP / IP stack, or other networking protocols