Senior Engineer - IP Design

The Opportunity

We're looking for the Wavemakers of tomorrow.

Alphawave Semi enables tomorrow's future by accelerating the critical data communication at the heart of our digital world – from seamless video streaming to AI to the metaverse and much more. Our technology powers product innovation in the most data-demanding industries today, including data centers, networking, storage, artificial intelligence, 5G wireless infrastructure, and autonomous vehicles. Customers partner with us for mission-critical data communication, our innovative technologies, and our proven track record. Together, we enable the next generation of digital technology.

Alphawave Semi is expanding its team in PCIe IP design and development! We are looking for talented RTL Design Engineers to contribute to enhance and develop our IP. This is an incredible opportunity to be part of the PCIe and CXL development cycle, from specification to design.

As an RTL Design Engineer, you will work in IP design and integration. You will be responsible for microarchitecture, RTL coding, create microarchitecture documents, Lint and Synthesis cycle and Timing closure. You will work with verification team on achieving test plan, the code & functional coverage.

What You'll Do

• Deliver standards-compliant PCIe IP block.
• Will work on Micro-architect and document the design.
• Develop RTL design using Verilog and / or System Verilog.
• Work closely with the verification team.
• Issue and track bug reports from launch to closure.
• Work with internal engineers to deliver designs for use.
• Collaborate with the team.
• You will be reporting to Principal Engineer of the Design team.

What You'll Need

'We have a flexible work environment to support and help employees thrive in personal and professional capacities'

As part of our commitment to the well-being and satisfaction of our employees, we have designed a comprehensive benefits package that includes :

Equal Employment Opportunity Statement

Alphawave Semi is an equal opportunity employer, welcoming all applicants regardless of age, gender, race, disability, or other protected characteristics. We value diversity and provide accommodations during the recruitment process.

Skills Required

LINT, C, Timing Closure, AMBA, Debugging Tools, Synthesis, Axi, Perl, Pcie, Verilog, AHB, System Verilog, Python, Tcl, Rtl Design