Senior Digital Design Engineer

About Analog Devices

Analog Devices, Inc. (NASDAQ : ) is a global semiconductor leader that bridges the physical and digital worlds to enable breakthroughs at the Intelligent Edge. ADI combines analog, digital, and software technologies into solutions that help drive advancements in digitized factories, mobility, and digital healthcare, combat climate change, and reliably connect humans and the world. With revenue of more than $9 billion in FY24 and approximately 24,000 people globally, ADI ensures today's innovators stay Ahead of What's Possible. Learn more at and on and .

Job Responsibilities :

• Designkey digital blocks such as accelerators / datapath IP in Verilog / System Verilog with built-in configurability to allow Power / Performance / Area tradeoffs
• Develop strong understanding of heterogenous processor cores & subsystems (A55 / M55 / M4 / U55 / RISC-V / DSP core, and associated infrastructure such as caches, interconnect fabric, GIC, DMA, MMU, Coresight Debug & Trace, TZC, SMPU, SPU) and their integration requirements
• Package Digital IP for seamless integration into design flow at different stages RTL / constraints / CDC waivers, timing wavers, DFT DRCs and waivers, software programming sequence etc
• Consolidate & curate digital IP for SPI / I2C / UART / JTAG and other slow serial interfaces & peripherals
• Evaluate 3 party IPs on Power / Performance / Area (PPA) and other key qualitative aspects such as design quality, Design For Testability, robustness of Design Verification (DV) practice, ease of integration and make recommendations
• Build expertise on complex interfaces, peripherals & protocols such as DDR, Ethernet, eMMC / SD, MIPI, Display Port, HDMI, PCIe, high speed D2D
• Develop and maintain catalog of digital IPs to enable ease of information sharing to customers across different BUs
• Develop User Guides for RTL Integration, Synthesis, DFT, PnR, Programming Sequence, characterization etc
• Establish evaluation flows for home-grown & 3 party IPs for consistent benchmarking of evaluation

Position Requirements :

Job Req Type : Experienced

Required Travel : Yes, 10% of the time

Shift Type : 1st Shift / Days

Skills Required

Static Timing Analysis, Spi, LINT, Uart, Design Verification, Verilog, Sd, System Verilog, Jtag, power analysis, I2c, Ethernet, Pcie, Dft, Ddr, HDMI