Static Timing Analysis Engineer - SoC Verification

Description :

Job Title : STA Engineer

Location : Bangalore, India

Experience : 4+ years

Job Overview :

We are seeking a highly skilled Design Verification and Static Timing Analysis (STA) Engineer with expertise in scan, ATPG, and SV UVM methodologies, as well as pre- and post-layout STA.

The ideal candidate will be responsible for ensuring the timing closure of complex SoCs, integrating IP-level constraints, and developing custom scripts for timing fixes.

Key Responsibilities :

Scan & ATPG :

• End-to-end experience in scan chain insertion, ATPG pattern generation, and post-silicon validation.
• Collaborate with design and verification teams to ensure full coverage and fault-free designs.

SV UVM Verification :

STA & Timing Closure :

Technical Skills :

Qualifications :

Why Join Us :

(ref : hirist.tech)