We’re Hiring : STA Engineer | 5–10 Years Experience | Bangalore & Hyderabad
Company : ACL Digital Company
Location : Bangalore & Hyderabad
Experience : 5 to 15 Years
Job Type : Full-Time
ACL Digital is looking for Senior Static Timing Analysis (STA) Engineers with solid experience in timing closure of advanced SoC designs.
If you’re an STA expert who thrives in fast-paced, technically challenging environments, we want to hear from you!
Responsibilities :
- Own and drive timing closure for complex SoC and ASIC designs across multiple technology nodes
- Perform full-chip and block-level timing analysis using industry-standard tools (Primetime, Tempus, etc.)
- Collaborate with RTL, synthesis, physical design, and verification teams to resolve timing violations
- Develop and maintain timing constraints (SDC), run STA checks (setup, hold, DRV, SI), and support ECO timing closure
- Contribute to methodology improvements and timing signoff strategies
- Report timing status, risks, and closure plans to technical leads and project stakeholders
Required Skills & Experience :
5–10 years of solid hands-on experience in STA and timing closureStrong expertise in timing concepts, constraints development, and signoff methodologyProficient in tools like Synopsys Primetime, Cadence TempusSolid understanding of clock tree design, DFT, multi-mode multi-corner (MMMC) analysisGood scripting skills (TCL / Perl / Python) to automate and debug flowsExperience with advanced nodes (7nm / 5nm / FinFET) is a plusStrong analytical, problem-solving, and communication skillsWhy Join Wafer Space?
Be part of a high-growth, innovation-driven semiconductor companyWork on state-of-the-art technologies with leading global clientsCollaborative and empowering work cultureCompetitive compensation and flexible work optionsOpportunity to grow your career in a technically challenging environmentInterested?
Send your resume to vaishnavi.suvarna@acldigital.com