Design Verification Lead - SoC / System Verilog

Lead Verification Engineer

Lead hands-on verification of complex SoC or large subsystems using UVM / SystemVerilog, owning plan-to-close execution through tapeout and silicon :

• Author verification plans from specs and micro-architecture; build reusable UVM environments from scratch at subsystem or SoC level.
• Develop constrained-random and directed tests, scoreboards, checkers, coverage models, and assertions (SVA).
• Drive coverage closure (functional, code, assertion), root-cause complex bugs, and work closely with RTL, architecture, and DFT.
• Enable SoC-level verification including interface / IP integration, coherency, low-power modes, resets / boot, and performance validation.
• Support silicon bring-up and correlation of failures to pre-silicon environments.

Must-have qualifications :

Nice to have :

Discounted / not counted experience :

(ref : hirist.tech)