Senior Serdes Architect

Senior SerDes Architect and Lead

Location : Bengaluru

About Omni Design Technologies

Omni Design Technologies is a leading provider of high-performance, ultra-low power IP cores, from 28nm down through advanced FinFET nodes, which enable differentiated system-on-chip (SoC), in applications ranging from 5G, wireline and optical communications, LiDAR, radar, automotive networking, AI, image sensors, and the internet-of-things (IoT).

Our data converter (ADC and DAC) IP cores range from 6-bit to 14-bit resolution and from a few MSPS to more than 100 GSPS sampling rates. Omni Design, founded in 2015 by semiconductor industry veterans, has an excellent track record of innovation and collaboration with customers to enable their success. The company is headquartered in Milpitas, California with additional design centers in Fort Collins-Colorado, Bangalore-India, Hyderabad-India, Dublin-Ireland, Boston-Massachusetts.

Senior SerDes Architect and Lead

Engineering – IP Architecture /

Full-time /

Hybrid

SerDes architect and development lead focused on PAM4 ADC and DAC based wireline technologies. The successful candidate in this role will work with customers to understand requirements, and will lead the development of high performance transistor level design starting from initial specification, through design and layout supervision, silicon evaluation and characterization to final product introduction to market.

Qualifications

10-20 years of experience in high-performance analog or mixed-signal IC development in advanced CMOS processes

Thorough familiarity with high-speed PAM4 architectures and topologies

Experience in designing high performance building block circuits such as bandgap reference, op-amp, comparators, oscillators, DLL, PLL, CTLEs, CDRs, etc.

Thorough understanding of equalization techniques (both analog and digital)

Must have a track record of successfully taking designs to production

Ability to work with customers to define products that address needs

Must have experience with evaluating silicon on bench and familiarity with standard lab equipment

Strong intuitive and analytical understanding of transistor-level circuit design including noise and mismatch analysis

Experience with analog and digital behavioral modeling, and / or synthesis of digital control blocks

Familiar with Cadence schematic capture, virtuoso, Spectre and / or HSPICE circuit simulation tools

MATLAB understanding would be preferred but not mandatory

Familiar with designing circuits for electromigration and ESD compliance in submicron CMOS process

Must be familiar with layout parasitic extraction tools and layout dependent impairments in advanced CMOS processes

Must be able to work independently, create and adhere to schedules

Must possess strong written and verbal communication skills with an ability to work with teams spread across geographic locations

Should be able to seek help proactively as well as share and pass on knowledge

Contact : Uday

Mulya Technologies

muday_bhaskar@yahoo.com

"Mining The Knowledge Community"