SOC RTL Engineering - Senior Manager

We Are :

At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation.

You Are :

You are a highly experienced and motivated professional with a solid background in SoC RTL Design. With over 12 years of experience, you have honed your skills in RTL Design, Lint, CDC, RDC, Synthesis, and Constraints Development. You possess a deep understanding of design concepts, ASIC flows, and stakeholder management. Your technical expertise allows you to debug and diagnose violations and errors, set up flows and methodologies for RTL Signoff tools, and develop timing constraints. You are an effective leader, capable of managing and growing a team, providing continuous feedback, and improving the quality of deliverables. Your excellent communication skills help you interact with customers, peers, and management to understand needs, report status, and resolve issues efficiently.

What You'll Be Doing :

• Manage and lead a team of 7-8 SoC / Subsystem RTL Design Engineers for various customer engagements.
• Work with Synopsys customers to understand their needs and define RTL Signoff and design scope and activities.
• Lead the team to perform various RTL Design and Signoff activities for SoC Subsystems such as SoC u-Architecture and Integration, RTL Design (Verilog / SystemVerilog), Lint, CDC, RDC, Synthesis, Constraints Development.
• Assist and mentor the team in day-to-day activities and grow the capabilities of the RTL Design team for future assignments.
• Review various results and reports to provide continuous feedback to the team and improve the quality of deliverables.
• Report status to management and provide suggestions to resolve any issues that may impact execution.
• Understand the complexity and requirements of RTL Quality Signoff and propose resource requirements to complete the activities.
• Work with peers to improve methodology and improve execution efficiency.
• Collaborate with other Synopsys teams including BU AEs and Sales to develop, broaden and deploy Tools.
• Train the team in design concepts and root-cause analysis.

The Impact You Will Have :

What You'll Need :

Who You Are :

The Team You'll Be A Part Of :

As part of the System Solutions Group (SSG), you will lead a team of experts in various Synopsys technologies to deliver architecture, design, verification, implementation, tools, and methodology to enable our customers to complete their most challenging SoC Design projects. Our work spans from sub-blocks to full turnkey end-to-end SoCs. Our customers range from start-ups to industry leaders, commercial companies, and government agencies.

Rewards and Benefits :

We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.

Skills Required

LINT, Synthesis, cdc, Timing Constraints, Debugging, Verilog, systemverilog, Rtl Design