FPGA Engineer - Static Timing Analysis

Description :

Job Title : FPGA Engineer (Architecture)

Location : Hyderabad

Experience : 4+ Years

Qualification : B.E / B.Tech / M.E / M.Tech in Electronics, Electrical, or related field

About the Role :

We are looking for a skilled FPGA Engineer (Architecture) with strong expertise in digital hardware design, FPGA development, and timing verification. The ideal candidate should have hands-on experience working with AMD (Xilinx) or Altera (Intel) FPGA platforms, and the ability to handle complete design-to-verification responsibilities independently or as part of a team.

Key Responsibilities :

• Design, implement, test, integrate, and deliver system-level digital designs for FPGA-based solutions.
• Perform architecture design and timing verification for FPGA blocks.
• Execute static timing analysis (STA) using tools such as Vivado and ensure design closure.
• Debug and resolve timing-related issues across multiple FPGA families.
• Perform manifold segmentation and partitioning of complex FPGA designs.
• Run and maintain internal scripts for performance testing, updating them as required.
• Ensure timely completion of design and verification tasks within project schedules.
• Collaborate closely with cross-functional teams for system integration and validation.
• Work effectively both independently and within a team-oriented environment.

Required Skills & Expertise :

Preferred Qualifications :

(ref : hirist.tech)