Static Timing Analysis Engineer

Looking for STA & Synthesis Engineer.

Exp.-3.5+yrs.

Job Location- Bangalore.

Notice Period- Prefer Immediate joiner or less notice period.

• Netlist and constraint sign in checks and validation.
• Responsible to complete synthesis till final-opt with DFT insertion
• Experience with sign-off Static Timing Analysis, Logic equivalency checks, and Static Low Power Checks
• Prime time constraint generation / development at Top level, full chip level and clean up.
• Multimode multi corner timing knowledge and timing closure at sub HM / block / top level.
• Top level timing closure with sign off STA in MMMC with Xtalk and OCV. Top level ECO implementation strategy development for netlist, RTL and timing level changes Scripting experience in Perl / TCL.

Regards,

Sneha

sneha.s@acldigital.com